1. Field of the Invention
The present invention relates in general to systems for testing integrated circuits and in particular to an apparatus for reducing power supply noise in an integrated circuit under test resulting from state transitions of the logic it implements.
2. Description of Related Art
An integrated circuit (IC) tester can concurrently test a set of ICs in the form of die on a semiconductor wafer. FIG. 1 is a block diagram illustrating a typical IC tester 10 connected through a probe card 12 to a set of similar IC devices under test (DUTs) 14 which may be formed on a semiconductor wafer. Tester 10 uses pogo pins 15 or other means to connect various input and output terminals to a set of contacts 16 on probe card 12. Probe card 12 includes a set of probes 18 for contacting input/output (I/O) pads 19 on the surface of each DUT 14 and provides conductive paths 20 linking contacts 16 to probes 18. The paths through probe card 12 allow tester 10 to transmit test signals to DUT 14 and to monitor output signals produced by the DUT. Since digital integrated circuits often include synchronous logic gates clocked in response to pulses of a periodic master clock signal (CLOCK), probe card 12 also provides a path 22 through which tester 10 may supply a CLOCK signal to each DUT 14. The test system also includes a power supply 24 for supplying power to DUTs 14 as they are being tested, and probe card 12 connects power supply 24 to a power input pad 26 of each DUT 14 through probes 18.
Each switching transistor within a DUT 14 has an inherent input capacitance, and in order to turn on or off the transistor, the transistor""s driver must either charge or discharge the transistor""s input capacitance. When a driver charges a transistor""s input capacitance it draws charging current from power supply 24. Once the transistor""s input capacitance is fully charged, its driver need only supply a relatively small amount of leakage current needed to keep the transistor""s input capacitance charged so that the transistor remains turned on or off. In DUTs implementing synchronous logic, most transistor switching occurs immediately after an edge of each CLOCK signal pulse. Thus immediately after each pulse of the CLOCK signal, there is a temporary increase in the power supply current I1 input to each DUT 14 to provide the charging current necessary to change the switching states of various transistors within the DUT. Later in the CLOCK signal cycle, after those transistors have changed state, the demand for supply current I1 falls to a xe2x80x9cquiescentxe2x80x9d steady state level and remains there until the beginning of the next CLOCK signal cycle.
The signal paths 28 through which probe card 12 connects power supply 24 to each DUT 14 have an inherent impedance represented in FIG. 1 by a resistance R1. Since there is a voltage drop between the output of power supply 24 and the power input 26 of DUT 14, the supply voltage input VB to DUT 14 is somewhat less than the output voltage VA of power supply 24, and although VA may be well-regulated, VB varies with the magnitude of current I1. After the start of each CLOCK signal cycle, the temporary increase in I1 needed to charge switching transistor input capacitance increases the voltage drop across R1, thereby temporarily reducing VB Since the dip in supply voltage VB occurring after each CLOCK signal pulse edge is a form of noise that can adversely affect the performance of DUTs 14, it is desirable to limit its magnitude and duration. We can limit that noise by reducing the reactance of the paths 28 between power supply 24 and DUTs 14, for example by increasing conductor size or by minimizing the length of path 28. However there are practical limits to the amount by which we can reduce that reactance.
We can also reduce power supply noise by placing a capacitor C1 on probe card 12 near the power supply input 26 of each DUT 14. FIG. 2 illustrates the behavior of supply voltage VB and current I1 at the power input 26 of IC 14 in response to a pulse of the CLOCK signal input to IC 14 when capacitor C1 is insufficiently large. Note that the temporary rise in I1 above its quiescent level IQ following an edge of the CLOCK signal at time T1 produces a temporary increase in voltage drop across R1 that in turn produces a temporary dip in supply voltage VC below its quiescent level VQ.
FIG. 3 illustrates the behavior of VB and I1 when capacitor C1 is sufficiently large. Between CLOCK signal pulses, when DUT 14 is quiescent, capacitor C1 charges to the quiescent level VQ of VB. Following a rising (or falling) edge of the CLOCK signal at time T1, when a DUT 14 temporarily demands more current, capacitor C1 supplies some its stored charge to DUT 14 thereby reducing the amount of additional current power supply 24 must provide to meet the increased demand. As may be seen in FIG. 3, the presence of C1 reduces the magnitude of the temporary voltage drop across R1 and therefore reduces the magnitude of the dip in the supply voltage VB input to the DUT 14.
For capacitor C1 to adequately limit variation in VB, the capacitor must be large enough to supply the needed charge to DUT 14 and must be positioned close to DUT 14 so that the path impedance between C1 and DUT 14 is very low. Unfortunately it is not always convenient or possible to mount a large capacitor on a probe card 12 near the power supply input terminal 26 of each DUT 14. FIG. 4 is a simplified plan view of a typical probe card 12. IC tester 10 resides above the probe card and the wafer containing DUTs 14 is held below the probe card. Since the I/O terminals of IC tester 10 of FIG. 1 are distributed over a relatively large area compared to the surface area of the wafer being tested, probe card 12 provides a relatively large upper surface 25 for holding the contacts 16 the tester accesses. On the other hand, the probes 18 (not shown) on the underside of probe card 12 that contact DUTs 14 on the wafer are concentrated under a relatively small central area 27 of probe card 12.
The path impedance between contacts 16 on the upper surface 25 of card 12 and the probes 18 under area 27 is a function of the distance between each contact 16 and its corresponding probe. To minimize the distance between capacitors C1 and the DUTs, the capacitors should be mounted on probe card 12 near (or above) the small central area 27. However when a wafer includes a large number of ICs to be tested or an IC having a large number of densely packed terminals, there is not enough space to mount the required number of capacitors C1 of sufficient size sufficiently close to central area 27.
During a test of an integrated circuit device under test (DUT) employing synchronous logic, the DUT experiences a temporary increase in its demand for power supply current after each successive leading or trailing edge of a clock signal input to the DUT. The DUT needs the extra current to charge input capacitance of transistors forming logic devices as they undergo state transitions in response to the clock signal edges. The invention limits variation in power supply voltage at the power input terminal of a DUT arising from the transient increase in power supply current following each clock signal pulse. The invention thereby reduces power supply noise at the DUT""s power input terminal.
In accordance with the invention, a charging current pulse is supplied to the DUT""s power input terminal after each clock signal edge to supplement a current continuously supplied by a main power supply during the test. The charging current pulse, suitably powered by an auxiliary power supply, reduces the need for the main power supply to increase its output current to meet the DUT""s increased demand. With the output current of the main power supply remaining substantially constant despite the DUT""s increased demand for current, the voltage drop across path impedance between the main power supply and the DUT remains substantially constant. Thus the supply voltage at the DUT""s power input terminal also remains substantially constant.
The amount of additional charging current a DUT requires after each clock signal edge varies depending on the number and nature of state transitions its internal logic devices undergo in response to the clock signal edge. Since a test of an IC requires the IC to carry out a predetermined sequence of state changes, the IC""s behavior during a test, including its demand for current during each clock signal edge, is predictable. The magnitude of the current pulse supplied after each clock signal edge is therefore adjusted to suit a predicted amount of additional charging current required by the DUT following each clock signal pulse. The prediction for the increase in current drawn by a DUT following each clock signal edge may be based, for example, on measurements of current drawn by a similar DUT under similar test conditions, or on simulations of the DUT undergoing an analogous test.
Although the amount of charging current an IC of a particular type may draw during any test cycle can be predicted with a fairly high degree of accuracy, the actual amount of additional charging current drawn by any given DUT of that type can be somewhat higher or lower than the predicted amount. Random process variations in the fabrication of ICs make all ICs behave somewhat differently, particularly with respect to the amount of charging current their transistors require during state changes. To compensate for such differences between DUTs, a feedback circuit is provided to monitor the voltage at the DUT""s power supply terminal and to appropriately scale the predicted magnitude of the current pulses so as to minimize variations in that voltage.
Thus the magnitude of the current pulse supplied to the power input terminal of a DUT following each clock signal cycle is a function of the predicted magnitude of the additional current drawn by a DUT of that type during that clock signal cycle, but the predicted pulse magnitude is scaled by feedback so as to adapt the prediction to accommodate the variation in charging current requirements for each particular DUT being tested.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.